**Figure 2A** and its equivalent circuit of **Figure 2B**.

Initially, with both switches open, there cannot be any primary or secondary currents flowing. Close the secondary load switch and then close the primary switch. Current flows through the primary winding. The L x dI(t)/dt action induces a voltage in the primary winding which opposes the source voltage. A voltage, Vsi, is also induced in the secondary winding causing secondary current to flow. The ampere-turns created by the secondary current work against the induced voltage that opposes the source voltage. Consequently, the source voltage supplies more current flow through the primary. Currents rapidly increase until either the secondary current or primary current encounters a current limitation. Examples of such limits are the secondary load and winding resistances limiting the secondary current or the source impedance and primary winding resistance and primary leakage inductance limiting the primary current. Once a limit is encountered, an equilibrium is quickly established except for the magnetizing current. The primary current has two components: Irs, the load current transformed (reflected) to the primary winding and Im, the magnetizing current. As in the no-load case, the magnetizing current starts at zero and increases over time. The pulse transformer must be switched off before saturation occurs.

In this example the load is resistive, there is no secondary leakage inductance, and there is no secondary winding capacitance; hence a purely resistive load current is reflected to the primary winding. The primary current is larger than it was in the no-load case, hence more voltage drop is expected across the primary winding resistance. Consequently less voltage, Vm, is available across Lm which results in less induced voltage in the secondary winding. Secondary current flow through the secondary winding resistance causes another voltage drop hence lower transformer output voltage. Under load, both the primary and secondary winding resistance contribute to a lower secondary voltage. The secondary winding resistance does not contribute to pulse droop.

The reflected load current, Irs, does not flow through the mutual inductance, Lm, but does flow through the primary leakage inductance, Lkp. Lkp restricts the flow of the primary current (hence reflected load current also). Consequently the reflected load current cannot immediately reach its full value (nor can the secondary current). It is effectively delayed. Until the reflected load current reaches its full value, a larger voltage drop will occur across Lkp than there was in the no-load case. This larger voltage diminishes in value over time. Consequently Vm exhibits a time delay in reaching peak voltage value. This delay is also seen in the secondary output voltage. This delay is known as rise time. Rise time is graphically illustrated in **Figure 4B**.